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fujitsu semiconductor microcontroller mb90m405 f 2 mc-16lx fa mi ly 16-bit microcontrollers hard wa re manual abstracts
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iii mb90m405 f 2 mc-16lx family 16-bit microcontrollers hardware manual abstracts ?1999 fujitsu limited printed in japan 1. circuit diagrams utilizing fujitsu products are included as a mean of illustrating typical semiconductor applications. complete information sufficient for construction proposes is not necessarily given. 2. the inform ation contained in this document has been carefully checked and is believed to be reliable. however, fujitsu assumes no responsibility for inaccuracies. 3. the information contained in this document does not convey any license under the copy right, patent right to trademarks claimed and owned by fujitsu. 4. fujitsu reserved the right to change products or specifications without notice. 5. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. 6. the products described in this document are not intended for use in equipment requiring high reliability, such as marine relays and medical life-support systems. for such applications, contact your fujitsu sales representative. 7. if the products and technologies described in this document are controlled by the foreign exchange and foreign trade control act established in japan, their export is subject to prior approval based on the said act.
iv preface n objective of manual and target audience the mb90m405 series is a general-purpose semiconductor device i n the f 2 mc-16lx family. it is a 16-bit single -chip microcontroller asic (application specific ic). this manual explains the function s and operation s of the mb90m405 series for engineers who design products using this device. how to read this manual n page o rganization a summary is given below the title of each section. a title of the main section is noted in the sub-section to recognize a current-reading section. n index organization (1) register map index the register map index format is similar to the i/o map and it allows search for the page explaining the bits of each register from the address, register abbreviation, register name, and resource macro name. use the register map index at searching for the register function when designing a resource macro. (2) pin function index the pin function index is similar to the explanation o f the pin function and it allows serch for the block diagram of each resource macro, the explanation o f the pin function, and notes from the package pin number, pin name, circuit type, and resource macro name. use the pin function index when creating the system board, etc. (the pin function index will be provided in the next revision of this manual ). n organization of notes and checks notes : reference information is given here. use this as a hint or note when using the mb90m405. this also gives a section (s) to refer. check : precautions when using the mb90m405 are given here. specification restrictions, etc . , are included.
1.1 features ................................ ................................ ............ 1-3 1.2 resources ................................ ................................ ......... 1-4 1.3 product lineup ................................ ................................ .. 1-5 1.4 block diagram ................................ ................................ ... 1-6 1.5 pin assignment ................................ ................................ . 1-7 1.6 pin description ................................ ................................ .. 1-8 1.7 i/o circuit type ................................ ............................... 1-11 1.8 notes on handling devices ................................ ............. 1-13 1.9 clock supply map ................................ ........................... 1-15 1.10 low power consumption mode ................................ ....... 1-16 1. general
mb90m405 f 2 mc-16lx family hardware manual 1- 2
general 1- 3 this chapter explains the features and basic specifications of the monolith (mb90m405). the mb90m405 series is a general-purpose 16-bit microcontroller developed for applications requiring fluorescent lamp panel control and contains 60 high-voltage withstand output pins required for a fluorescent lamp. as with the original f 2 mc-8l and f 2 mc-16l families, the instruction system inherits the at architecture, and has extended high-level language interface instructions and the extended addressing modes, enhanced multiplication/division instructions (signed), and enhanced bit processing . in addition, a 32-bit accumulator enables handle long word processing . 1.1 features clock: pll clock multiplication circuit built-in operating clock (pll clock) generated by dividing original oscillation by 2 or by multiplying original oscillation by 1 to 4 (2.1 mhz to 16.8 mhz at original oscillation of 4.2 mhz) . can be selected . minimum instruction execution time is 59.5 ns ( when the original oscillation is 4.2 mhz, the pll clock is generated by multiplying the original oscillation by 4, and vcc = 3 v) . it is possible to generate an external output as a clock output by dividing the original oscillation by 16, 32, 64, or 128. maximum memory space: 16 mbytes 24-bit addressing in memory space instruction system suited for controller applicable data types (bit, byte, word, long-word) various addressing modes: 23 types high code efficiency high-precision operation with 32-bit accumulator signed multiplication and division instructions and enhanced reti instruction powerful instruction system applicable to high-level language (c) or multitasking system stack pointer symmetric instruction set and barrel shift instruction program patch function (2-address pointer) shortened execution time : 4-byte instruction queue powerful interrupt function ( e ight programmable priority levels) powerful interrupt function for 32 interrupt factors data transfer function ( e xtended intelligent i/o service function: 16 channels max imum ) low-power consumption ( s tandby mode) sleep mode ( stops cpu operating clock) pseudo-time r mode ( stops everything except original oscillation and time-base timer) stop mode ( stops original oscillation) cpu intermittent operati on mode package qfp -100 (fpt-100p-m06: 0.65 mm pin pitch) process cmos technology
mb90m405 f 2 mc-16lx family hardware manual 1- 4 1.2 resources i/o port : 26 pins max imum (all 26 pins can also serve as resource pins) . 18-bit time-base timer : 1 channel watchdog timer : 1 channel 16-bit reload timer : 3 channels 16-bit free-run timer : 1 channel 16-bit output compare : 1 channel 16-bit i nput capture : 2 channels when the count value of the 16-bit free-run timer matches the setting value of the output compare, the timer is cleared and an interrupt request is issued . s erial i/o : 2 channels uart : 2 channels clock-synchronous serial transfer (i/o extended serial) can be used. the direction of the shift clock level can be selected arbitrarily (msb or lsb). dtp/external interrupt (4 channels) start e xtended intelligent i/o services by an external input, and generate an external interrupt . delayed interrupt generation module a task-switching interrupt request is generated. 8-/10-bit a/d converter (16 channel) 8- or 10-bit resolution can be selected. fl controller enables fl driver control . (the auto display control is performed for 32 digits max. and 59 segments max.) 1 to 32 digits can be set ( can be set on a digit-by-digit basis) . the dimmer can be set. enables led driver control (auto display control is performed for 16 segments max imum ) . the auto display control can be performed for 16 segments max. at 1/2 duty. time r clock divider the original oscillation can be divided by 32, 64, 128, or 256.
general 1- 5 1. 3 product lineup table 1-1 lists the monolith ( mb90m4 05) series product lineup. function s other than the rom/ram capacity are shared . table 1- 1 mb90m4 05 series product lineup product name mb90mv4 05 mb90mf4 08 mb90m4 08 mb90m4 07 classification evaluate flash type rom mass-produced product (mask rom) rom capacity not provided 128 kbytes 96 kbytes ram capacity 4 kbytes 4 kbytes 4 kbytes cpu f unction count of basic instructions: 351 minimum instruction execution time: 59.5 ns ( at original oscillation of 4.2 mhz, with pll clock generated by multiplying original oscillation by 4) a ddressing type s : 23 program patch function: 2-address pointer maximum memory space: 16 mbytes port i/o port (cmos) 26 pins (all of 26 pins also serve as resource pins) fl controller 60 fl output pins can be used ( under led control, 43 fl output pins and 17 led control pins are required). enables fl driver control and led driver control can be performed. under fl driver control, the dimmer can be set for both digits and segments. serial i/o (uart) c an also be used as the clock-synchronous method extended i/o serial. a dedicated baud rate generator is built-in . four channels are built-in (two channels also serve as uart channels). 16-bit reload timer 16-bit reload timer operation (toggle output or one-shot output can be selected . ) an event count function can be selected. three channels are built-in . 16-bit free-run timer 16-bit output compare x 1 channel (for clearing free-run timer) 16-bit input capture x 2 channels 8-/10-bit a/d converter 8-/10-bit resolution x 16 channels (input multiplex) minimum conversion time: 6.2 s ( at internal operation of 16 mhz) time r clock divider the external input clock can be divided and output to the outside. clock divi sion rate s : 16, 32, 64, or 128 (programmable) external interrupt four independent channels (also serve for a/d input) interrupt factor: l ? h edge, h ? l edge, l level, or h level low power consumption mode sleep mode, stop mode, cpu intermittent mode, or pseudo-time r mode process cmos package pga256 qfp-100 (0.65 mm pitch) operating voltage 3.3 v 0.3 v (16.8 mhz: 4.2 mhz multiplied by 4)
mb90m405 f 2 mc-16lx family hardware manual 1- 6 1. 4 block diagram fip0/led0 to fip16/led16 fip17 to fip59 fl controller timer clock divider v-ram 8-/10-bit a/d converter serial i/o ( ch 2 ) external interrupt input controller rom (96/128 kb) ram (4 kb) clock controller cpu controller x0 ,x1 rstx md2 ,1,0 16-bit free-run timer 16-bit input capture ( c h 0, 1) 16-bit output compare i 2 c interface 16-bit reload timer ( c h 0, 1, 2) fmc - 16lx bus pa0/an0/tmck pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 pb0/an8 pb1/an9 pb2/an10 pb3/an11/si2 pb4/an12/sc2/tin pb5/an13/so2/to pb6/an14/int3 pb7/an15/int2 p80/ic0/int0 p81/ic1/int1 p82/si0 p83/sc0 p84/so0 p85/si1 p86/si2 p87/si3 p90/sda/so3 p91/scl/sc3 port a port b port 8 port 9 uart ( c h.0,1) serial i/o ( ch 3 ) fig. 1.1 block diagram (mb90m4 05 )
general 1- 7 1. 5 pin assignment f pt -100 p-m06 pin assignment fip16/led16 1 fip17 2 fip18 3 fip19 4 fip20 5 fip21 6 fip22 7 fip23 8 fip24 9 fip25 10 vss-io 11 fip26 12 fip27 13 fip28 14 fip29 15 fip30 16 fip31 17 fip32 18 fip33 19 fip34 20 fip35 21 fip36 22 vdd-fip 23 fip37 24 fip38 25 fip39 26 fip40 27 fip41 28 fip42 29 fip43 30 31 fip44 32 fip45 33 fip46 34 fip47 35 fip48 36 fip49 37 fip50 38 fip51 39 fip52 40 fip53 41 fip54 42 vss-io 43 fip55 44 fip56 45 fip57 46 fip58 47 fip59 48 vkk 49 md0 50 md1/vdd-vft 60 59 58 57 56 55 54 53 52 51 p82/si0 p81/ic1/int1 p80/ic0/int0 md2 p86/sc1 p85/si1 p84/so0 p83/sc0 p90/sda/so3 p87/so1 70 69 68 67 66 65 64 63 62 61 pa0/an0/tmck avss avcc p91/scl/sc3 pa4/an4 pa3/an3 pa2/an2 pa1/an1 pa6/an6 pa5/an5 80 79 78 77 76 75 74 73 72 71 pb2/an10 pb1/an9 pb0/an8 pa7/an7 pb5/an13/so2/to0 rstx pb4/an12/sc2/tin0 pb3/an11/si2 pb7/an15/int3 pb6/an14/int2 82 x0 81 vss-cpu 84 vcc-cpu 83 x1 86 fip1/led1 85 fip0/led0 88 fip3/led3 87 fip2/led2 90 fip5/led5 89 fip4/led4 92 fip7/led7 91 fip6/led6 94 fip9/led9 93 fip8/led8 96 fip11/led11 95 fip10/led10 98 fip13/led13 97 fip12/led12 100 fip15/led15 99 fip14/led14
mb90m405 f 2 mc-16lx family hardware manual 1- 8 1.6 pin description table s 1- 2, 1- 3 and 1- 4 list the pin name, function, circuit type, and reset-time state/function. table 1- 2 pin description pin no. qfp-100m06 pin name circuit type state/function at reset function 8 2, 83 x0 , x1 a oscillation state o scillation input pins. 77 rstx b reset input external reset input pin fip0 to fip15 this function is selected when the fl driver is enabled. 85 to 100 led0 to led15 this function is selected when the led driver is enabled. fip16 this function is selected when the fl driver is enabled. 1 led16 this function is selected when the led driver is enabled. 2 to 10 12 to 19 fip17 to fip33 c 20 to 22 24 to 41 43 to 47 fip34 to fip59 d vkk pull-down output d edicated pins for the fl driver output. p80 g eneral-purpose i/o port ic0 e xternal trigger input pin for input capture 0 52 int0 e xternal factor input pin for external interrupt input 0 this pin is only accepted when it is enabled by the en0 bit. p 81 g eneral-purpose i/o port ic1 e xternal trigger input pin for input capture 1 53 int1 e xternal factor input pin for external interrupt input 1 this pin is only accepted when it is enabled by the en1 bit. p82 g eneral-purpose i/o port 54 si0 s erial data input pin for serial i/o channel 0 this pin is always effective when channel 0 is under input operation. p83 g eneral-purpose i/o port 55 sc0 s erial clock i/o pin for serial i/o channel 0 this pin is effective when the channel-0 clock output is enabled. p 84 g eneral-purpose i/o port 56 so0 s erial data output pin for serial i/o channel 0 this pin is effective when the channel-0 serial data output is enabled. p85 g eneral-purpose i/o port 57 si1 s erial data input pin for serial i/o channel 1 this pin is always effective when channel 0 is under input operation. p86 g eneral-purpose i/o port 58 sc1 s erial clock i/o pin for serial i/o channel 1 this pin is effective when the channel-0 clock output is enabled. p87 this pin is a general-purpose i/o port. 59 so1 s erial data output pin for serial i/o channel 1 this pin is effective when the channel-0 serial data output is enabled. p90 g eneral-purpose i/o port ( however, the n ch is open drain . ) sda d ata i/o pin for the i 2 c interface. this function is effective when operation of the i 2 c interface is enabled. also, set the port output to the hi-z state when operating the i 2 c interface. 60 so3 g hi-z s erial data output pin for serial i/o channel 3 this pin is effective when the channel-3 serial data output is enabled.
general 1- 9 table 1- 3 pin description pin no. qfp-100m06 pin name circuit type state/function at reset function p91 g eneral-purpose i/o port ( however, the n ch is open drain . ) scl c lock i/o pin for the i 2 c interface this function is effective when operation of the i 2 c interface is enabled. also, set the port output to the hi-z state when operating the i 2 c interface. 61 sc3 g hi-z s erial clock i/o pin for serial i/o channel 3 this pin is effective when the channel-3 clock output is enabled. pa0 g eneral-purpose i/o port an0 a nalog input pin 0 for the a/d converter this function is effective when the analog input specification is enabled (using ader). 64 tmck t ime r clock output pin this pin is only effective when output is enabled. this pin is null when analog input is enabled using ader. pa1 to pb2 g eneral-purpose i/o port 65 to 74 an1 to an10 a nalog input pins (1 to 10) for the a/d converter this function is effective when the analog input specification is enabled (using ader). pb3 g eneral-purpose i/o port an11 a nalog input pin (11) for the a/d converter this function is effective when the analog input specification is enabled (using ader). 75 si2 s erial data input pin for serial i/o channel 2 this pin is always effective when channel 2 is under input operation. pb4 g eneral-purpose i/o port an12 a nalog input pin (12) for the a/d converter this function is effective when the analog input specification is enabled (using ader). sc2 s erial clock i/o pin for serial i/o channel 2 this pin is effective when the channel-2 clock output is enabled. 76 tin0 e xternal clock input pin for reload timer channel 0 this pin is enabled when the external clock input is effective (ader takes precedence). pb5 g eneral-purpose i/o port an13 a nalog input pin (13) for the a/d converter this function is effective when the analog input specification is enabled (using ader). so2 s erial data output pin for serial i/o channel 2 this pin is effective when the channel-2 serial data output is enabled. 78 to0 e xternal event output pin for reload timer channel 0 this pin is effective when the external event output is enabled (ader takes precedence). pb6 and pb7 g eneral-purpose i/o port an14 and an15 a nalog input pins (14, 15) for the a/d converter this function is effective when the analog input specification is enabled (using ader). 79, 80 int2 and int3 f analog input e xternal factor input pins for external interrupt inputs 2 and 3 these pins are accepted only when they are enabled using the en2 bit and the en3 bit. 62 avcc vcc power input pin for the analog macro 63 avss h vss power input pin for the analog macro 48 vkk ? power input p ower pin on the pull-down side at high-voltage withstand output.
mb90m405 f 2 mc-16lx family hardware manual 1- 10 table 1- 4 pin description pin no. qfp-100m06 pin name circuit type state/function at reset function 49 md0 i nput pin for specifying the operating mode connect this pin to vcc. also, always switch this pin to vss at boot programming to flash memory. 50 md1/vdd-vft i nput pin for specifying the operating mode connect this pin to vcc. this pin also serves as the vdd-vft pin. 51 md2 b mode pin i nput pin for specifying the operating mode connect this pin to vss. also, always switch this pin to vcc at b oot programming to flash memory. 11, 42 vss-io p ower (0 v: gnd) input pins for i/o 23 vdd-fip p ower (3 v: vcc) input pin for the fip 81 vss-cpu p ower (0 v: gnd) input pin for the controller 84 vcc-cpu ? power input p ower (3 v: vcc) input pin for the controller
general 1- 1. 7 i/o circuit type table s 1-5 and 1-6 show the circuit type for each pin. table 1- 5 i/o circuits x1 x0 classification a oscillator oscillation feedback resistor: about 1 m w r b hysteresis input pin resistor value : about 50 k w (typ) c p- ch open-drain output - high-voltage withstand port output i ol = -25 ma d p- ch open-drain output - high-voltage withstand port output i ol = - 12 ma circuit remarks xout pout r kk v kk when using the pin as a normal port, connect a diode clamp, etc. , to prevent application of vkk voltage to the pin at output of the l level (see h andling notes ). pout r kk v kk when using the pin as a normal port, connect a diode clamp, etc. , to prevent application of vkk voltage to the pin at output of the l level (see h andling notes ). standby control signal
mb90m405 f 2 mc-16lx family hardware manual 1- 12 table 1- 6 i/o circuits e cmos h ysteresis i/o pin cmos-level output cmos hysteresis input (the input cutoff function is provided in the standby mode.) i ol = 4 ma f g n- ch open drain output cmos level hysteresis input (the input cutoff function is provided in the standby mode . ) h analog/ cmos h ysteresis i/o pin cmos-level output cmos h ysteresis input (the input cutoff function is provided in the standby mode.) analog input (analog input is effective when the corresponding bit of ader is 1.) i ol = 4 ma classification circuit remarks standby control pout hysteresis input standby control nout analog input r hysteresis input standby control nout r in unlike the cmos i/o pin, the re is no p - ch transistor at this pin. consequently , even when an external voltage is applied to this pin with the power to the device set to off, no current flow s to the device power ( vcc-io/ vcc-cpu). analog power input protector hysteresis input pout nout r
general 1- 13 1. 8 notes on handling devices (1) be careful not to exceed the maximum rated voltage (prevention of la t ch up). for a cmos ic, latch-up may occur if a voltage higher than vcc or a voltage lower than vss is applied to the i/o pin other than medium - /high-voltage withstand i/o pin s , or when a voltage that exceeds the rated voltage is applied between vcc and vss. latch up rapidly increases the power current, and the device may be destroyed by heat. when using the device, take care not to exceed the maximum rating. also, take care that the analog power ( avcc) and the analog input do not exceed the digital power ( vcc) when turning the ac/dc power on or off. (2) design the device so the supply voltage is as stable as possible. a sudden change in the power voltage may cause a malfunction even within the operating assurance range of the vcc power supply voltage. for safety, the vcc ripple (p-p) of the commercial frequency (50/60 mhz) must be 10% or less of the standard vcc value, and the transient fluctuation at instantaneous power switching must be 0.1 v/ms or less. also, take counter measures to power noise, etc. (3) notes at power -on the voltage rise time at power -on must be 50 s or more (0.2 to 2.7 v). ( 4 ) setting unused in put pins leaving unused input pins open may cause a malfunction. therefore, these pins must be set to the pull- up or pull-down state. (5) handling of power pins for a/d converter even w hen the a/d converter is not used, connect the pins so that the following relationships are established : av cc = v cc , av ss = v ss . ( 6 ) notes on using external clock even w hen an external clock is used, the oscillation stabilization wait time is required at the power-on reset or the cancellation of the stop mode. in this case, drive the x0 pin only and l eave the x1 pin open. example of using external clock x0 x1 mb90 m 405 series open
mb90m405 f 2 mc-16lx family hardware manual 1- 14 (7) power pins when two or more vcc pins and vss pins are provided , pins are designed to be at the same electric potential are internally connected to the device to prevent malfunction s such as latch-up . however, always connect all same electric potential pins to power and ground outside the device to prevent decrease of extraneous and radiation the malfunction of the strobe signal due to a ground level rise , and follow the standards on total output current, etc. also, consider to connect ing the pins to vcc and vss of this device at the lowest possible impedance from the current supply source (it is recommended to connect a bypass capacitor of about 0.1 m f of the device between vcc and vss) . (8) a pplication sequence for power analog inputs for a/d converter apply the digital power ( vcc) first, and then apply the power ( avcc) and analog inputs (an0 to an15) for the a/d converter. disconnect the power and analog inputs for the a/d converter first, and then disconnect the digital power ( vcc). also, do no t allow the input voltage to exceed avcc even when using a pin shared with an analog input as an input port ( s imultaneous application and disconnection of analog power and digital power is allowed) . (9) output of high-voltage withstand output pin (circuit type c or d) when the high-voltage withstand output pin (circuit type is c or d) is used as an ordinary output port, the port outputs the vkk pin voltage pull-down value at the l level output . in this case, the vkk pin level voltage is applied to the external circuit, so it is recommended to add a diode clamp circuit as shown in the figure below. pout r kk v kk diode clamp circuit
general 1- 15 1.9 clock supply map the clock supply map for this device ( m onolith : mb90m405) is shown below. hclk: oscillation clock mclk: main clock (operating clock : clock generated by dividing oscillation clock by 2) pclk: pll clock clock generator oscillator selector time r clock divider time-base timer pll multiplication circuit pclk selector divide-by-2 circuit mclk hclk 1 2 3 4 watchdog timer resources fl controller 16-bit reload timer 10-bit a/d converter 8-bit serial i/o 6-bit free-run timer 16-bit input capture 16-bit output compare i 2 c communications interface cpu (f 2 mc-16lx) rom/ram (memory) x0 x1
mb90m405 f 2 mc-16lx family hardware manual 1- 16 1. 10 this section provides an overview of the low power consumption mode. the onolith (mb90m405) has the following modes that stop various functions and clocks chapter 4 . ? relationships between operating modes and power operating mode main clock pll clock cpu resources timer clock pll run operates operates operates operates operates main run operates stops operates operates operates pll s leep operates operates stops operates * operates main sleep operates stops stops operates * operates pseudo-time operates stops stops stops operates stop stops stops stops stops stops in the above table, the power consumption decreases as the operating mode goes down from the top of the table . in the pll run mode, operation is performed on the pclk generated by multiplying the original oscillation by 1 to 4. in the main run mode , operation is performed on the mclk generated by dividing the original oscillation by 2. *: in the sleep mode, the cpu stops, so resources cannot be accessed from the cpu.
1 may 19, 2000 preliminary version 1 mb90m405 series electric specification table n electrical characteristics 1. absolute maximum rating (v ss-cpu = v ss-io = avss = 0.0 v) rated value parameter symbol min. max. unit remarks v cc-cpu v ss C 0.3 v ss + 4.0 v power supply pin for control circuit v dd-fip v ss C 0.3 v ss + 4.0 v power supply pin for fip av cc v ss C 0.3 v ss + 4.0 v vcc > avcc* 1 power supply voltage v kk v cc C 45 v cc + 0.3 v pull-down side power supply pin for high voltage resistance output. v i vss C 0.3 vss + 4.0 v * 2 input voltage ? i2 vss C 0.3 vss + 5.5 v * 3 v o vss C 0.3 vss + 4.0 v * 2 output voltage v o2 vss C 0.3 vss + 5.5 v * ? (open drain output) "l" level max. output current i ol 15ma* 4 , * 5 "l" level avg. output current i olav 4ma average value (operating current operating rate) * 5 "l" level max. overall output current s i ol 100 ma * 5 "l" level avg. overall output current s i olav 50ma average value (operating current operating rate) * 5 i oh C15 ma * 4 , * 5 i ohfip1 C27 ma fip00 to fip33 pins "h" level max. output current i ohfip2 C14 ma fip34 to fip59 pins "h" level avg. output current i ohav C4ma average value (operating current operating rate) * 5 "h" level max. overall output current s i oh C100 ma * 5 s i ohav C50 ma average value (operating current operating rate) * 5 "h" level avg. overall output current s i ohfipav C180 ma average value (operating current operating rate) * 6 p d_cpu 300 mw for cpu_chip individual operation power consumption p d_fl 1176 mw for fl_chip individual output operation operating temperature t a C40 +85 c storage temperature t stg C55 +150 c data sheet
2 *1: av cc should not exceed v cc when turning on the power supply. *2: v i and v o should not exceed v cc + 0.3 v. *3: the 5 v withstandable voltage pin for i 2 c. applies to p90/sda, p91/scl only. *4: the maximum output current is standard at the peak value of the corresponding 1 pin. *5: excludes currents on the fip00 to fip59 pins. *6: fip00 to fip59 pins are targeted. cautions: 1. the v cc specification in the table means: v dd-fip = v dd-vft = v cc-cpu . use with the same power supply level as the three pins described above. also, v ss means: v ss-io = v ssCcpu . connect this pin to the gnd. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltage to this high impedance circuit.
3 2. recommended conditions (v ss-io = v ss-cpu = avss = 0.0 v) rated value parameter symbol min. max. unit remarks v cc-cpu 3.0 3.6 v under normal operation v dd-fip 3.0 3.6 v under normal operation power supply voltage vcc 2.5 3.6 v maintains status of stop operation v ihs 0.8 vcc vcc + 0.3 v cmos hysterisis input pins other than i 2 c v ihs2 0.8 vcc 5.8 v cmos hysterisis input pins of i 2 c (5 v withstandable voltage)* 1 h level input voltage v ihm vcc C 0.3 vcc + 0.3 v md pin input v ils vss C 0.3 0.2 vcc v cmos hysterisis input pins other than i 2 c v ils2 vss C 0.3 0.2 vcc v cmos hysterisis input pins of i 2 c (5 v withstandable voltage)* 1 l level input voltage v ilm vss C 0.3 vss + 0.3 v md pin input operation temperature t a C40 +85 c *1: on the 1st es product of mb90mf408, the withstandable voltage is 3 v (can be used up to 4.5 v at the test lab level). caution: the v cc specification in the table means: v dd-fip = v dd-vft = v cc-cpu . use with the same power supply level as the three pins described above. also, v ss means: v ss-io = v ss C cpu . connect this pin to the gnd.
4 3. dc specifications (t a = C40 to 85 c, v dd-fip = v dd-vft = v cc-cpu = av cc = 3.0 to 3.6 v, v ss-io = v ss-cpu = av ss = 0 v) rated value parameter symbol pin test condition min. typ . max. unit remarks v oh5 v cc = 3.3 v i oh5 = C23 ma vcc C 2.5 v v oh4 fip00 to fip33 v cc = 3.3 v i oh4 = C12 ma vcc C 1.3 v v oh3 v cc = 3.3 v i oh3 = C12 ma vccv C 2.0 v v oh2 fip34 to fip59 v cc = 3.3 v i oh2 = C5 ma vcc C 1.0 v v oh1 sda/scl i oh1 = C4 ma 5.5 v open drain pin * 2 output h voltage v oh0 all output pins other than the above i oh = C2.0 ma vcc C 0.5 vccC 0.3 v v ol1 sda/scl i ol = 15 ma 0.5 0.8 v output l voltage v ol all output pins other than the above i ol = 2.0 ma 0.2 0.4 v input leak current i il input pins other than fip00-59 v cc = 3.0 v ( v s ? MB90MV405 (f targeted standard values)* 1 vcc = 3.3 v, and internal operation at 16 mhz, and a/d operation 45 55 ma mb90mf408 MB90MV405 (f targeted standard values)* 1 i cc flash programming/erasing 40 50 ma mb90mf408 power supply current i ccs vcc vcc = 3.3 v, and internal operation at 16 mhz, and sleep operation 15 20 ma * 1 (continue)
5 (continued) rated value parameter symbol pin test condition min. typ . max. unit remarks power supply current i cch t a = +25 c, and operation stopped 15 20 m a (targeted standard values) pull-up resistor r up rstx 20 65 200 k w r dw1 md2 20 65 200 k w pull-down resistor r dw1 fip00 to fip59 when there are settings 80 120 160 k w *1: current values that are specified do not include the consumption current on the high withstandable voltage pins. they indicate the consumption current internally on the circuit. *2: on the 1st es product of mb90mf408, the max. standard value is 3.6 v (can be used up to 4.5 v at the test lab level). notes: 1. the v cc specification in the table means: v dd-fip = v dd-vft = v cc-cpu . use with the same power supply level as the three pins described above. also, v ss means: v ss-io = v ss C cpu . connect this pin to the gnd. 2. there can be changes in the current value according to improvements in performance. the measuring condition of the power supply current is the external clock.
6 pll operating guaranteed range relationship between internal-operation clock frequency and power supply voltage internal clock f cp (mhz) 16 3 1.5 3.0 3.6 power supply voltage vcc (v) pll operating guaranteed range relationship between original oscillation frequency and internal-operation clock frequency original oscillating clock f cp (mhz) 4 multipulation 3 multipulation 2 multipulation 1 multipulation non- multipulation 816 3 8 4 16 12 internal clock f cp (mhz) 12 6 4 3 2 1.5 6 9
7 4. a/d conversion unit electrical characteristics (t a = C40 to +85 c, v cc-cpu avcc = 3.0 v to 3.6 v, v ss-cpu = v ss-io = avss = 0 v) rated value parameter symbol pin min. typ. max. unit remarks resolution 10 bit can switch to 8 bits overall error 3.0 lsb non-linearity error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an15 avss C1.5 lsb a ? ss +0.5 lsb avss +2.5 lsb mv full scale transition voltage v fst an0 to an15 avcc C3.5 lsb avcc C1.5 lsb avcc +0.5 lsb mv 1lsb= avcc/1022 conversion time ( sampling + compare ) 98 t cp * 2 ns 16 mhz operation sampling time 32 t cp * 2 ns 16 mhz operation compare time 66 t cp * 2 ns 16 mhz operation analog port input current i ain an0 to an15 10 m a analog input voltage v ain an0 to an15 0 avcc v reference voltage avcc 3.0 avcc v i a avcc 5ma power supply current i ah avcc 5 m a * 1 i r avcc 100 200 m a reference voltage supply current i rh avcc 5 m a * 1 channel differences an0 to an15 4lsb *1: when not operating a/d converter, this is the current (v cc-cpu = av cc = 3.3 v) when the cpu is stopped. *2: t cp means: 1/internal operating frequency. when the internal operating frequency is 16 mhz, t cp is 1/16 mhz = 62.5 ns. notes: 1. the reference l value is fixed at av ss ; the reference h value is fixed at av cc . the error is relatively large as the av cc becomes smaller. 2. analog input external circuit output impedance should use the following conditions. external circuit output impedance 10 k w 3. if the external circuit output impedance is too high, there maybe insufficient time for sampling of the analog voltage. mb90m407/m408 r= about 1.5 k w on c= about 30 pf mb90mf408, MB90MV405 r = about 3.0 k w on c = about 65 pf r on comparator analog input c analog input circuit model diagram note: numeric values herein should be used as a guide.
8 6. handling device preventing latch-up latch-up may occur in cmosic when a voltage higher than v cc-cpu or lower than v ss-cpu is applied to the input or output pins, or a voltage exceeding the rated value is applied between v cc-cpu and v ss-cpu . latch- up may cause a rapid increase in the supply current, sometimes resulting in thermal damage to the device. therefore, keep the used voltage within the maximum ratings. when turning the power on and off the analog supply voltage (av cc ) analog input should not exceed the digital supply voltage (v cc-cpu ). voltage supplies should be stabilized. a sudden change of the power supply voltage may cause a malfunction even within the guaranteed range of operation of the v cc-cpu power supply voltage. for reference of stabilization, voltage variations are recommended to be restrained so that v cc-cpu ripple variations (p-p values) are below 10% of the standard v cc-cpu value in commercial frequencies (50 to 60 hz), and so that transient variation is below 0.1 v/ms in sudden changes during power switchovers. precautions when turning on the power supply ensure a minimum of 50 m s (between 0.2 to 2.7 v) for voltage rise times when turning on the power supply to prevent malfunction of the built-in power reduction circuit. handling of unused input pins leaving unused input pins open may cause a malfunction. therefore, these pins should be connected to a pull-up or a pull-down resistor. handling of a/d converters power supply pins connect power supply pins with av cc = v cc-cpu , av ss = v cc-io even when not using the a/d converters. precautions when using the external clock oscillating stability waiting time is required when resetting from the power on reset, stop mode when using the external clock. order of turning on the power turn off the digital power supply (v cc-cpu ) after turning off the a/d converter power supplie (av cc, av ss ) and analog input (an0 to an15). do not allow the input voltage to exceed av cc when using the analog input pins as an input port.

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